User:Divyanshu

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Divyanshu Bandil Delhi University -- Netaji Subhas Institute of Technology, Dwarka, Delhi, India

Project plan

Following is a snapshot the latest-version text from bandil:ascend/ply-compilers/docs/ply-ascend-dev-plans.txt

We have a number of simple technical goals for this ascend via python work, discussed later. These will contribute to a number of conceptual goals:

  • Free the ascend language from its GPL'd C implementation for market reasons.
  • Free the ascend language implementation from global variables altogether--proper use of python objects should assure this, as would proper use of Cobjects if we had time for rewrites w/proper testing.
  • Create a framework for experimenting with syntax changes that have ascend4syntax equivalents which are considered 'klunky' or have semantics which isnot in the documented specification of ascend4.
  • Create a framework for writing model export formatting plug-ins withpython rather than C, which has notably painful string handling.

Divyanshu Bandil technical goals, gsoc 2011:

  • ply-a4: a parser, possibly instantiator, in python, as the 'unmodified' base for parsing proposed extensions to ascend4 and/or python translators to other languages.
  • ply-a4-if: extension syntax experiment adding if and generating standard a4 from it. A simpler starting example for this is to implement the FIX and FREE operators as translations to the proper solver_var attribute handling syntax.

Stretch targets:

  • ply-a5: a new-syntax experiment, probably more c-like. Possibly based on plycparser.
  • performance: compare instantiation and evaluation performance of python vs C. Ben has a hypothesis that we can preserve the excellent performance and scalability of ascend relation instantiation and evaluation (while using python) if we try. Would require a python implementation of our instantiator; ascend's for loops are not procedural, so they don't map neatly to python classes as proxies for ascend models.
  • binary translator: export python-ascend instance trees to C/C++/fortran code generators for use in generating parallelism-supported computations. Some overlap with GPU projects.

Progress reports

Final Report

Added a detailed final report in the Progress folder with future possible development.

See bandil:ascend/ply-compilers/Progress/Final.txt for details.

22 Aug

Transformation code for FIX/FREE statement AST fragments completed


Overall Progress

COMPLETED TASKS

Skeletal lexer and parser - scanner.py and ascParse.py

Creation of AST node classes - AST_Generator and related cfg files

Development of mechanism for keeping track of position of various tokens - position.py and ascMain.py

Development of mechanism for converting the AST to string form - ASTtoString.py and StringAST.txt

Integration of AST nodes in parser for units, dimensions and fractions and converting them to string form - ascParse_AST.py and asc_AST.py, units.py


IN PROGRESS

Integration of other AST nodes in parser in progress - ascParse_AST.py

Development of tree visitor class


Divyanshu is keeping a record of his work in plain text files.

See bandil:ascend/ply-compilers/Progress for details.

14 Jul

Added code for creating a string form of ascend AST and writing it to a text file.

See bandil:ascend/ply-compilers/Progress for details.

27 Jun

Ben Allan responds bandil:ascend/ply-compilers/Progress/comments.june.25.

25 Jun

From bandil:ascend/ply-compilers/Progress/June25.txt:

Current State We have got a decent way to generate asts through a AST Generator class and a configuration file. A lot of statements having simple structures in the corresponding C code have been replicated in the cfg file. Also a class for position tracking has been created in position.py. Position of a particular rule, production or token will be stored in an object of this class while parsing.

To Do

  • Similar Node generator classes for expr_types,units and dimensions
  • Integration of the AST nodes into the parser file for AST construction

Issues

  1. Implementation of SlisthasWhat and AddContext functions for some statements. Should we make changes in the ASTGenerator Class to accommodate for it or should we create a modified_State_types.py which implements these functions?
  2. Regarding ForOrder, ForKind, FlowControl, and ExternalKind enums - It would we good if we create a 'unified class' for them and just mention 'enum' in beginning of the attribute name in the cfg file which will force it to look for its value in the unified class by specifying in ASTGeneretor class.

18 Jun

Ben Allan reports: we have a skeleton parser in place with ply, now we're on to the harder parts: produce AST, create operations to validate AST, create operations to rewrite AST, create operations to generate output code from AST.

9 Jun

From bandil:ascend/ply-compilers/Progress/June9.txt: For debugging purpose, print statements has been included as action codes for some grammar rules in the parser file. It has been checked with some existing models from the models directory and many bugs removed. The lexer/parser seems to work fine.

6 Jun

bandil:ascend/ply-compilers/Progress/June6.txt

Pre-acceptance notes

Model of a simple diode circuit with dc voltage source and a resistance in series. 

REQUIRE "atoms.a4l";

MODEL diode;
	(*variables*)
	
	V IS_A voltage;
	R IS_A resistance;
	VD IS_A voltage;
	Is IS_A current;
	I IS_A current;

	(*equations*)
	(V - VD)/R = Is * ((exp(VD/0.043478261)) - 1);
	I = Is * ((exp(VD/0.043478261)) - 1);

	
METHODS
	(*Fixing values for a simple circuit connecting a diode , a dc voltage and a resistor in series*)
	
	METHOD on_load;
		RUN default_self;
		RUN values;
		RUN specify;
	END on_load;

	METHOD specify;
		FIX V , R , Is;
	END specify;	

	METHOD values;
		V := 5 {volt};
		R := 1000 {ohm};
		Is := 1e-10 {amp};
	END values;
	
	METHOD default_self;
		VD := 0.7 {volt};
	END default_self;

END diode;
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Model Diode


Model of a transistor with fixed collector voltage and collector current. 

REQUIRE "atoms.a4l";

MODEL BJT 
(	(* Biasing Voltages *)
	VCC WILL_BE voltage;
	VBB WILL_BE voltage;
	VEE WILL_BE voltage;
	
	VE WILL_BE voltage; (* Emitter Voltage *)
	VB WILL_BE voltage; (* Base Voltage *)
	VC WILL_BE voltage; (* Collector Voltage *)

	RC WILL_BE resistance;
	RE WILL_BE resistance;
	RB WILL_BE resistance;
		
	IE WILL_BE current; (* Emitter Current *)
	IB WILL_BE current; (* Base Current *)
	IC WILL_BE current; (* Collector Current *)

	(*BJT parameters*)
	bF WILL_BE variable;
	bR WILL_BE variable;
);
	aF IS_A variable;
	aR IS_A variable;
	VT IS_A voltage;
	Is IS_A current; (*Scaling Current*)
	
	(* Equations *)
	
	aF = bF/(1 + bF);
	aR = bR/(1 + bR);
	
	(*Ebers-Moll Model Equations*)
	IE = (Is/aF)*(exp((VB - VE)/VT) - 1) - (Is)*(exp((VB - VC)/VT) - 1);
	IC = (Is)*(exp((VB - VE)/VT) - 1) - (Is/aR)*(exp((VB - VC)/VT) - 1);
	IB = (Is/bF)*(exp((VB - VE)/VT) - 1) + (Is/bR)*(exp((VB - VC)/VT) - 1);

	(VE - VEE)/RE = (Is/aF)*(exp((VB - VE)/VT) - 1) - (Is)*(exp((VB - VC)/VT) - 1);
	(VCC - VC)/RC = (Is)*(exp((VB - VE)/VT) - 1) - (Is/aR)*(exp((VB - VC)/VT) - 1);
	(VB - VBB)/RB = (Is/bF)*(exp((VB - VE)/VT) - 1) + (Is/bR)*(exp((VB - VC)/VT) - 1);	

METHODS

	METHOD specify;
		FIX Is;
		FIX VT;
	END specify;

	METHOD values;
		Is := 1e-15 {amp};
		VT := 0.025 {volt};
	END values;

	METHOD bound_self;
	END bound_self;

	METHOD bound_all;
		RUN bound_self;
	END bound_all;

	METHOD scale_self;
	END scale_self;

	METHOD scale_all;
		RUN scale_self;
	END scale_all;
		
END BJT;

MODEL BJT1;
	
	VE IS_A voltage; (* Emitter Voltage *)
	VB IS_A voltage; (* Base Voltage *)
	VC IS_A voltage; (* Collector Voltage *)

	(* Biasing Voltages *)
	VCC IS_A voltage;
	VBB IS_A voltage;
	VEE IS_A voltage;

	RC IS_A resistance;
	RE IS_A resistance;
	RB IS_A resistance;
	
	IE IS_A current; (* Emitter Current *)
	IB IS_A current; (* Base Current *)
	IC IS_A current; (* Collector Current *)

	bF IS_A variable;
	bR IS_A variable;

	BJT11 IS_A BJT( VCC, VBB, VEE, VE, VB, VC,
			RC, RE, RB,
			IE, IB, IC,
			bF, bR);

METHODS

	METHOD on_load;
		RUN default_self;
		RUN values;
		RUN specify;
	END on_load;

	METHOD specify;
		RUN BJT11.specify;
		FIX bF;		
		FIX bR;
		FIX VCC;
		FIX VEE;
		FIX VB;
		FIX RB;
		FIX VC , IC;
	END specify;

	METHOD values;
		RUN BJT11.values;
		bF := 100;
		bR := 0.02;
		VCC := 15 {volt};
		VEE := -15 {volt};
		VB := 0.0 {volt};
		RB := 1e-100 {ohm}; (*RB set very low not zero because division by zero not possible*)
		VC := 5 {volt};
		IC := 0.002 {amp};
	END values;

	METHOD default_self;
		VE := VB - 0.7{volt};
	END default_self;

END BJT1;
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Screenshot of solving various parameters of a transistor
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