User:Divyanshu

Divyanshu Bandil Delhi University -- Netaji Subhas Institute of Technology, Dwarka, Delhi, India

Project plan

(copied by Jpye 00:41, 5 May 2011 (UTC))

We have a number of simple technical goals for this ascend via python work, discussed later. These will contribute to a number of conceptual goals:

• Free the ascend language from its GPL'd C implementation for market reasons.

• Free the ascend language implementation from global variables altogether--proper use of python objects should assure this, as would proper use of Cobjects if we had time for rewrites w/proper testing.

• Create a framework for experimenting with syntax changes that have ascend4syntax equivalents which are considered 'klunky' or have semantics which isnot in the documented specification of ascend4.

• Create a framework for writing model export formatting plug-ins withpython rather than C, which has notably painful string handling.

Divyanshu Bandil technical goals, gsoc 2011:

ply-a4: a parser, possibly instantiator, in python, as the 'unmodified' base for parsing proposed extensions to ascend4 and/or python translators to other languages.

ply-a4-if: extension syntax experiment adding if and generating standard a4 from it. A simpler starting example for this is to implement the FIX and FREE operators as translations to the proper solver_var attribute handling syntax.

Stretch targets:

ply-a5: a new-syntax experiment, probably more c-like. Possibly based on plycparser.

performance: compare instantiation and evaluation performance of python vs C. Ben has a hypothesis that we can preserve the excellent performance and scalability of ascend relation instantiation and evaluation (while using python) if we try. Would require a python implementation of our instantiator; ascend's for loops are not procedural, so they don't map neatly to python classes as proxies for ascend models.

Binary translator: export python-ascend instance trees to C/C++/fortran code generators for use in generating parallelism-supported computations. Some overlap with GPU projects.

Pre-acceptance notes

Model of a simple diode circuit with dc voltage source and a resistance in series.

REQUIRE "atoms.a4l";

MODEL diode;
	(*variables*)
	
	V IS_A voltage;
	R IS_A resistance;
	VD IS_A voltage;
	Is IS_A current;
	I IS_A current;

	(*equations*)
	(V - VD)/R = Is * ((exp(VD/0.043478261)) - 1);
	I = Is * ((exp(VD/0.043478261)) - 1);

	
METHODS
	(*Fixing values for a simple circuit connecting a diode , a dc voltage and a resistor in series*)
	
	METHOD on_load;
		RUN default_self;
		RUN values;
		RUN specify;
	END on_load;

	METHOD specify;
		FIX V , R , Is;
	END specify;	

	METHOD values;
		V := 5 {volt};
		R := 1000 {ohm};
		Is := 1e-10 {amp};
	END values;
	
	METHOD default_self;
		VD := 0.7 {volt};
	END default_self;

END diode;

Error creating thumbnail: File missing

Model Diode

Model of a transistor with fixed collector voltage and collector current.

REQUIRE "atoms.a4l";

MODEL BJT 
(	(* Biasing Voltages *)
	VCC WILL_BE voltage;
	VBB WILL_BE voltage;
	VEE WILL_BE voltage;
	
	VE WILL_BE voltage; (* Emitter Voltage *)
	VB WILL_BE voltage; (* Base Voltage *)
	VC WILL_BE voltage; (* Collector Voltage *)

	RC WILL_BE resistance;
	RE WILL_BE resistance;
	RB WILL_BE resistance;
		
	IE WILL_BE current; (* Emitter Current *)
	IB WILL_BE current; (* Base Current *)
	IC WILL_BE current; (* Collector Current *)

	(*BJT parameters*)
	bF WILL_BE variable;
	bR WILL_BE variable;
);
	aF IS_A variable;
	aR IS_A variable;
	VT IS_A voltage;
	Is IS_A current; (*Scaling Current*)
	
	(* Equations *)
	
	aF = bF/(1 + bF);
	aR = bR/(1 + bR);
	
	(*Ebers-Moll Model Equations*)
	IE = (Is/aF)*(exp((VB - VE)/VT) - 1) - (Is)*(exp((VB - VC)/VT) - 1);
	IC = (Is)*(exp((VB - VE)/VT) - 1) - (Is/aR)*(exp((VB - VC)/VT) - 1);
	IB = (Is/bF)*(exp((VB - VE)/VT) - 1) + (Is/bR)*(exp((VB - VC)/VT) - 1);

	(VE - VEE)/RE = (Is/aF)*(exp((VB - VE)/VT) - 1) - (Is)*(exp((VB - VC)/VT) - 1);
	(VCC - VC)/RC = (Is)*(exp((VB - VE)/VT) - 1) - (Is/aR)*(exp((VB - VC)/VT) - 1);
	(VB - VBB)/RB = (Is/bF)*(exp((VB - VE)/VT) - 1) + (Is/bR)*(exp((VB - VC)/VT) - 1);	

METHODS

	METHOD specify;
		FIX Is;
		FIX VT;
	END specify;

	METHOD values;
		Is := 1e-15 {amp};
		VT := 0.025 {volt};
	END values;

	METHOD bound_self;
	END bound_self;

	METHOD bound_all;
		RUN bound_self;
	END bound_all;

	METHOD scale_self;
	END scale_self;

	METHOD scale_all;
		RUN scale_self;
	END scale_all;
		
END BJT;

MODEL BJT1;
	
	VE IS_A voltage; (* Emitter Voltage *)
	VB IS_A voltage; (* Base Voltage *)
	VC IS_A voltage; (* Collector Voltage *)

	(* Biasing Voltages *)
	VCC IS_A voltage;
	VBB IS_A voltage;
	VEE IS_A voltage;

	RC IS_A resistance;
	RE IS_A resistance;
	RB IS_A resistance;
	
	IE IS_A current; (* Emitter Current *)
	IB IS_A current; (* Base Current *)
	IC IS_A current; (* Collector Current *)

	bF IS_A variable;
	bR IS_A variable;

	BJT11 IS_A BJT( VCC, VBB, VEE, VE, VB, VC,
			RC, RE, RB,
			IE, IB, IC,
			bF, bR);

METHODS

	METHOD on_load;
		RUN default_self;
		RUN values;
		RUN specify;
	END on_load;

	METHOD specify;
		RUN BJT11.specify;
		FIX bF;		
		FIX bR;
		FIX VCC;
		FIX VEE;
		FIX VB;
		FIX RB;
		FIX VC , IC;
	END specify;

	METHOD values;
		RUN BJT11.values;
		bF := 100;
		bR := 0.02;
		VCC := 15 {volt};
		VEE := -15 {volt};
		VB := 0.0 {volt};
		RB := 1e-100 {ohm}; (*RB set very low not zero because division by zero not possible*)
		VC := 5 {volt};
		IC := 0.002 {amp};
	END values;

	METHOD default_self;
		VE := VB - 0.7{volt};
	END default_self;

END BJT1;

Error creating thumbnail: File missing

Screenshot of solving various parameters of a transistor