User:Divyanshu: Difference between revisions
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(copied by [[User:Jpye|Jpye]] 00:41, 5 May 2011 (UTC)) | (copied by [[User:Jpye|Jpye]] 00:41, 5 May 2011 (UTC)) | ||
<source lang= | <source lang=sh> | ||
We have a number of simple technical goals for this ascend via python work, | We have a number of simple technical goals for this ascend via python work, | ||
discussed later. These will contribute to a number of conceptual goals: | discussed later. These will contribute to a number of conceptual goals: | ||
Revision as of 00:41, 5 May 2011
Divyanshu Bandil Delhi University -- Netaji Subhas Institute of Technology, Dwarka, Delhi, India
Project plan
(copied by Jpye 00:41, 5 May 2011 (UTC))
Invalid language.
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a4c, abap, abc, abnf, actionscript, ada, agda, alan, algol, ampl, amtrix, applescript, arc, arm, as400cl, ascend, asciidoc, asp, aspect, assembler, ats, autohotkey, autoit, avenue, awk, ballerina, bat, bbcode, bcpl, bibtex, biferno, bison, blitzbasic, bms, bnf, boo, c, carbon, ceylon, charmm, chill, chpl, clean, clearbasic, clipper, clojure, clp, cmake, cobol, coffeescript, coldfusion, conf, cpp2, critic, crk, crystal, cs_block_regex, csharp, css, d, dart, delphi, diff, dockerfile, dts, dylan, ebnf, ebnf2, eiffel, elixir, elm, email, erb, erlang, euphoria, exapunks, excel, express, factor, fame, fasm, felix, fish, fortran77, fortran90, frink, fsharp, fstab, fx, gambas, gdb, gdscript, go, graphviz, haml, hare, haskell, haxe, hcl, html, httpd, hugo, icon, idl, idlang, inc_luatex, informix, ini, innosetup, interlis, io, jam, jasmin, java, javascript, js_regex, json, jsp, jsx, julia, kotlin, ldif, less, lhs, lilypond, limbo, lindenscript, lisp, logtalk, lotos, lotus, lua, luban, makefile, maple, markdown, matlab, maya, mercury, meson, miranda, mod2, mod3, modelica, moon, ms, msl, mssql, mxml, n3, nasal, nbc, nemerle, netrexx, nginx, nice, nim, nix, nsis, nxc, oberon, objc, ocaml, octave, oorexx, org, os, oz, paradox, pas, pdf, perl, php, pike, pl1, plperl, plpython, pltcl, po, polygen, pony, pov, powershell, pro, progress, ps, psl, pure, purebasic, purescript, pyrex, python, q, qmake, qml, qu, r, rebol, rego, rexx, rnc, rpg, rpl, rst, ruby, rust, s, sam, sas, scad, scala, scilab, scss, shellscript, slim, small, smalltalk, sml, snmp, snobol, solidity, spec, spn, sql, squirrel, styl, svg, swift, sybase, tcl, tcsh, terraform, tex, toml, tsql, tsx, ttcn3, txt, typescript, upc, vala, vb, verilog, vhd, vimscript, vue, wat, whiley, wren, xml, xpp, yaiff, yaml, yaml_ansible, yang, zig, znn
Pre-acceptance notes
Model of a simple diode circuit with dc voltage source and a resistance in series.
REQUIRE "atoms.a4l"; MODEL diode; (*variables*) V IS_A voltage; R IS_A resistance; VD IS_A voltage; Is IS_A current; I IS_A current; (*equations*) (V - VD)/R = Is * ((exp(VD/0.043478261)) - 1); I = Is * ((exp(VD/0.043478261)) - 1); METHODS (*Fixing values for a simple circuit connecting a diode , a dc voltage and a resistor in series*) METHOD on_load; RUN default_self; RUN values; RUN specify; END on_load; METHOD specify; FIX V , R , Is; END specify; METHOD values; V := 5 {volt}; R := 1000 {ohm}; Is := 1e-10 {amp}; END values; METHOD default_self; VD := 0.7 {volt}; END default_self; END diode;
Model of a transistor with fixed collector voltage and collector current.
REQUIRE "atoms.a4l"; MODEL BJT ( (* Biasing Voltages *) VCC WILL_BE voltage; VBB WILL_BE voltage; VEE WILL_BE voltage; VE WILL_BE voltage; (* Emitter Voltage *) VB WILL_BE voltage; (* Base Voltage *) VC WILL_BE voltage; (* Collector Voltage *) RC WILL_BE resistance; RE WILL_BE resistance; RB WILL_BE resistance; IE WILL_BE current; (* Emitter Current *) IB WILL_BE current; (* Base Current *) IC WILL_BE current; (* Collector Current *) (*BJT parameters*) bF WILL_BE variable; bR WILL_BE variable; ); aF IS_A variable; aR IS_A variable; VT IS_A voltage; Is IS_A current; (*Scaling Current*) (* Equations *) aF = bF/(1 + bF); aR = bR/(1 + bR); (*Ebers-Moll Model Equations*) IE = (Is/aF)*(exp((VB - VE)/VT) - 1) - (Is)*(exp((VB - VC)/VT) - 1); IC = (Is)*(exp((VB - VE)/VT) - 1) - (Is/aR)*(exp((VB - VC)/VT) - 1); IB = (Is/bF)*(exp((VB - VE)/VT) - 1) + (Is/bR)*(exp((VB - VC)/VT) - 1); (VE - VEE)/RE = (Is/aF)*(exp((VB - VE)/VT) - 1) - (Is)*(exp((VB - VC)/VT) - 1); (VCC - VC)/RC = (Is)*(exp((VB - VE)/VT) - 1) - (Is/aR)*(exp((VB - VC)/VT) - 1); (VB - VBB)/RB = (Is/bF)*(exp((VB - VE)/VT) - 1) + (Is/bR)*(exp((VB - VC)/VT) - 1); METHODS METHOD specify; FIX Is; FIX VT; END specify; METHOD values; Is := 1e-15 {amp}; VT := 0.025 {volt}; END values; METHOD bound_self; END bound_self; METHOD bound_all; RUN bound_self; END bound_all; METHOD scale_self; END scale_self; METHOD scale_all; RUN scale_self; END scale_all; END BJT; MODEL BJT1; VE IS_A voltage; (* Emitter Voltage *) VB IS_A voltage; (* Base Voltage *) VC IS_A voltage; (* Collector Voltage *) (* Biasing Voltages *) VCC IS_A voltage; VBB IS_A voltage; VEE IS_A voltage; RC IS_A resistance; RE IS_A resistance; RB IS_A resistance; IE IS_A current; (* Emitter Current *) IB IS_A current; (* Base Current *) IC IS_A current; (* Collector Current *) bF IS_A variable; bR IS_A variable; BJT11 IS_A BJT( VCC, VBB, VEE, VE, VB, VC, RC, RE, RB, IE, IB, IC, bF, bR); METHODS METHOD on_load; RUN default_self; RUN values; RUN specify; END on_load; METHOD specify; RUN BJT11.specify; FIX bF; FIX bR; FIX VCC; FIX VEE; FIX VB; FIX RB; FIX VC , IC; END specify; METHOD values; RUN BJT11.values; bF := 100; bR := 0.02; VCC := 15 {volt}; VEE := -15 {volt}; VB := 0.0 {volt}; RB := 1e-100 {ohm}; (*RB set very low not zero because division by zero not possible*) VC := 5 {volt}; IC := 0.002 {amp}; END values; METHOD default_self; VE := VB - 0.7{volt}; END default_self; END BJT1;